# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:02:24  DECEMBER 16, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION "4.0 SP1"
set_global_assignment -name VHDL_FILE mire_digitale3_13.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_14 -to adresse\[18\]
set_location_assignment PIN_4 -to adresse\[17\]
set_location_assignment PIN_5 -to adresse\[14\]
set_location_assignment PIN_6 -to adresse\[13\]
set_location_assignment PIN_8 -to adresse\[8\]
set_location_assignment PIN_9 -to adresse\[9\]
set_location_assignment PIN_11 -to i
set_location_assignment PIN_12 -to Q
set_location_assignment PIN_16 -to adresse\[11\]
set_location_assignment PIN_17 -to adresse\[10\]
set_location_assignment PIN_2 -to data\[7\]
set_location_assignment PIN_19 -to data\[6\]
set_location_assignment PIN_20 -to data\[5\]
set_location_assignment PIN_21 -to data\[4\]
set_location_assignment PIN_24 -to data\[3\]
set_location_assignment PIN_25 -to data\[2\]
set_location_assignment PIN_26 -to data\[1\]
set_location_assignment PIN_27 -to data\[0\]
set_location_assignment PIN_28 -to adresse\[0\]
set_location_assignment PIN_29 -to adresse\[1\]
set_location_assignment PIN_31 -to adresse\[2\]
set_location_assignment PIN_33 -to adresse\[4\]
set_location_assignment PIN_34 -to adresse\[3\]
set_location_assignment PIN_36 -to adresse\[5\]
set_location_assignment PIN_37 -to adresse\[6\]
set_location_assignment PIN_39 -to adresse\[7\]
set_location_assignment PIN_40 -to adresse\[15\]
set_location_assignment PIN_41 -to adresse\[12\]
set_location_assignment PIN_18 -to adresse\[16\]
set_location_assignment PIN_43 -to clk_16
set_location_assignment PIN_44 -to sel_phase
set_location_assignment PIN_1 -to test_enb

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name TOP_LEVEL_ENTITY mire_digitale3_13

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7064SLC44-5"

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL output from Quartus II)"

# Assembler Assignments
# =====================
set_global_assignment -name MAX7000S_JTAG_USER_CODE 313

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------